The present application relates generally to semiconductor devices, and more particularly to vertical-transport fin field effect transistors (VT-FinFETs) and their methods of fabrication.
Fully-depleted devices such as fin field effect transistors (FinFETs) are candidates to enable scaling of next generation gate lengths to 14 nm and below. Fin field effect transistors (FinFETs) present a three-dimensional architecture where the transistor channel is raised above the surface of a semiconductor substrate, rather than locating the channel at or just below the surface. With a raised channel, the gate can be wrapped around the sides of the channel, which provides improved electrostatic control of the device.
The manufacture of FinFETs typically leverages a self-aligned process to produce extremely thin fins, e.g., 10 nm thick, or less, on the surface of a substrate using selective-etching techniques. A gate structure is then deposited to contact multiple surfaces of each fin to form a multi-gate architecture. However, while the thin channel enables robust control of the device, its shape limits the flow of current when the device is turned on. In this regard, multiple fins are typically arranged in parallel to provide higher drive strength.
Vertical-transport FETs are devices where the source-drain current flows in a direction normal to the substrate surface. In vertical-transport FinFET devices, the fin defines the channel with the source and drain regions located at opposing (i.e., upper and lower) ends of the fin. An advantage of the vertical-transport field effect transistor is that the channel length is not defined by lithography, but by methods such as epitaxy or layer deposition, which enable precise dimensional control. A further advantage is that the maximum gate length is not limited by the transistor density or spacing.
A limitation associated with a vertical-transport FET architecture is a low effective channel width (Weff). In contrast to a conventional FinFET where the fin height can be increased to provide additional channel cross section, increasing the fin dimension in a vertical-transport structure either disadvantageously consumes additional real estate or increases the distance, and hence the resistance, between the source and drain. Accordingly, it would be advantageous to provide a robust, vertical-transport FinFET manufacturing process and associated structure that are compatible with existing circuit designs, while enabling high drive strength.